1. Field
Example embodiments relate to a phase change memory device and a method of fabricating the same, and more particularly, to a phase change memory device consuming less electric power and/or having improved current-voltage (I-V) characteristics and a method of fabricating the same.
2. Description of the Related Art
Semiconductor memory devices may be classified as volatile memory devices and non-volatile memory devices according to their capability to retain data when a power supply is disconnected. A dynamic random access memory (DRAM) and a static random access memory (SRAM) are examples of a volatile memory device. Such a memory device stores data as a logic 0 or a logic 1 according to a stored electric potential. DRAM may be able to store many electric charges because a DRAM regularly refreshes. Therefore, research has been conducted to increase the surface area of a capacitor electrode of the DRAM. However, increasing a surface area of a capacitor electrode may make it difficult to integrate a DRAM device.
A flash memory device may include a semiconductor substrate, a gate insulation layer, a floating gate, a dielectric film and/or a gate pattern as a control gate stacked on a semiconductor substrate. A flash memory cell may record or erase data by tunneling electrons through the gate insulation layer. To tunnel the electrons, an operating voltage greater than a supply voltage may be required. Accordingly, a booster circuit may be required to provide the operating voltage for recording and/or erasing the flash memory device.
Therefore, research has been conducted to develop a new memory device having a simple structure, high integrity and/or non-volatile characteristics and/or providing a random access scheme. Recently, a phase change memory device has been spotlighted as a next generation memory device. A phase change memory device uses a phase change material. The phase change material becomes amorphous or crystalline according to the amplitude of a supplied current, that is, Joule heating, and has distinct electric conductivity according to whether it is in an amorphous state or a crystalline state.
FIG. 1 is a graph illustrating a method of operating a phase change memory device according to the conventional art. A method of recording and erasing data in a phase change memory cell will be explained with reference to the graph in FIG. 1. In the graph, the horizontal axis represents time and the vertical axis represents the temperature of a phase change material layer.
Referring to FIG. 1, if the phase change material layer is heated to a temperature higher than a melting temperature Tm of the phase change material and then suddenly cooled as shown in a first curve 1, the phase material layer enters an amorphous state. On the other hand, if the phase change material layer is heated to a temperature lower than the melting temperature Tm and higher than a crystallization temperature Tc of the phase change material over a time T2, which is longer than T1 as shown in a second curve 2 of the graph, the heated phase change material layer is annealed and enters a crystalline state. The resistivity of the phase change material layer in the amorphous state is greater than the resistivity of the phase change material layer in the crystalline state. Accordingly, stored data can be discriminated as logic 1 or logic 0 by detecting a current flowing through the phase change material layer in a read mode. Chalcogenide materials are widely used as the phase change material. Among the chalcogenide materials, a compound material layer (GST) containing germanium (Ge), antimony (Sb) and tellurium (Te) is widely used in phase change memory.
FIG. 2 is a cross sectional view of a phase change memory device according to the conventional art. Referring to FIG. 2, the conventional phase change memory device includes a bottom conductive layer 10, a top conductive layer 18, a thin film type of a phase change material layer 16 interposed between the bottom conductive layer 10 and the top conductive layer 18, and/or a contact unit 14 electrically connecting the bottom conductive layer 10 and the phase change material layer 16. The bottom conductive layer 10 and side surfaces of the contact unit 14 may be surrounded by an insulation layer 12. A contacting surface of the contact unit 14 may be electrically coupled to the phase change material layer 16. A transistor 5 may be electrically connected to the bottom conductive layer 10 and a current may be supplied to the bottom conductive layer 10, the top conductive layer 18 and the phase change material layer 16 interposed between the bottom conductive layer 10 and the top conductive layer 18 through the transistor 5. The current supplied to the top conductive layer 18 may flow through the phase change material layer 16, the contact unit 14, the bottom conductive layer 10 and the transistor 5.
In the phase change memory device, if the current flows between the bottom conductive layer 10 and the top conductive layer 18, the current flows to the phase change material layer 16 through the contact unit 14 and the contacting surface 20. According to the Joule heating caused by the current, the phase change material around the contacting surface 20 changes from a crystalline state to an amorphous state. A current required to change the phase change material from the crystalline state depends on the size of the contacting surface 20. That is, the smaller the contacting surface 20 is, the less current that is required to change the phase change material from the crystalline state. However, the configuration of a conventional phase change memory device having a thin film type phase change material is limited when the size of the contacting surface 20 is reduced.